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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3850 group is the 8-bit microcomputer based on the 740 family core technology. The 3850 group is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, and A-D converter.
FEATURES
qBasic machine-language instructions ...................................... 71 qMinimum instruction execution time .................................. 0.5 s (at 8 MHz oscillation frequency) qMemory size ROM ................................................................... 8K to 24K bytes RAM ..................................................................... 512 to 640 byte qProgrammable input/output ports ............................................ 34 qInterrupts ................................................. 14 sources, 14 vectors qTimers ............................................................................. 8-bit ! 4 qSerial I/O ....................... 8-bit ! 1(UART or Clock-synchronized) qPWM ............................................................................... 8-bit ! 1 qA-D converter ............................................... 10-bit ! 5 channels qWatchdog timer ............................................................ 16-bit ! 1 qClock generating circuit ..................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator)
qPower source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In high-speed mode .................................................. 2.7 to 5.5 V (at 4 MHz oscillation frequency) In middle-speed mode ............................................... 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode .................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) qPower dissipation In high-speed mode .......................................................... 34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................ 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) qOperating temperature range.................................... -20 to 85C
APPLICATION
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P44/INT3/PWM P43/INT2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY P26/SCLK P25/TxD P24/RxD P23 P22 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13/(LED0) P14/(LED1) P15/(LED2) P16/(LED3) P17/(LED4)
Package type : FP ........................... 42P2R-A (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin shrink plastic-molded DIP)
Fig. 1 M38503M4-XXXFP/SP pin configuration
M38503M4-XXXFP M38503M4-XXXSP
2
Reset input VSS RESET
18 15 21 1
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK DIAGRAM
Fig. 2 Functional block diagram
VCC CNVSS
Main-clock input XIN
Main-clock output XOUT
19
20
Sub-clock Sub-clock input output
XCIN
XCOUT
Clock generating circuit
CPU
RAM ROM
X
Prescaler 12(8)
A
Timer 1( 8 ) Timer 2( 8 ) Timer X( 8 ) Timer Y( 8 )
Y
Prescaler X(8)
S PC H PS
CNTR1
PCL
CNTR0
Prescaler Y(8)
Watchdog timer
Reset
A-D converter (10)
PWM (8)
SI/O(8)
XCOUT XCIN INT0- INT3
P4(5) P3(5)
P2(8)
P1(8)
P0(8)
23 45678
38 39 40 41 42
9 10 11 12 13 1416 17
22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37
I/O port P4
I/O port P3
I/O port P2
I/O port P1
I/O port P0
VREF
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
AVSS
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description Pin VCC, VSS CNVSS RESET XIN XOUT Name Power source CNVSS input Reset input Clock input Clock output Functions *Apply voltage of 2.7 V - 5.5 V to Vcc, and 0 V to Vss. *This pin controls the operation mode of the chip. *Normally connected to VSS. *Reset input pin for active "L." *Input and output pins for the clock generating circuit. *Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. *When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *CMOS 3-state output structure. *P13 to P17 (5 bits) are enabled to output large current for LED drive. *8-bit CMOS I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level. *P20, P21, P24 to P27: CMOS3-state output structure. *P22, P23: N-channel open-drain structure. * Sub-clock generating circuit I/O pins (connect a resonator)
Function except a port function
P00-P07
I/O port P0
P10-P17 P20/XCOUT P21/XCIN P22 P23 P24/RxD P25/TxD P26/SCLK P27/CNTR0/ SRDY P30/AN0- P34/AN4 P40/CNTR1 P41/INT0- P43/INT2 P44/INT3/PWM
I/O port P1
I/O port P2
* Serial I/O function pin
* Serial I/O function pin/ Timer X function pin I/O port P3 *8-bit CMOS I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure. I/O port P4 *8-bit CMOS I/O port with the same function as port P0. *CMOS compatible input level. *CMOS 3-state output structure. * Timer Y function pin * Interrupt input pins * Interrupt input pin * PWM output pin * A-D converter input pin
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product M3850 3 M 4
XXX FP Package type FP : 42P2R-A package SP : 42P4B package SS : 42S1B-A package
ROM number Omitted in some types.
ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes
9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
Fig. 3 Part numbering
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3850 group as follows:
Packages
42P4B..........................................42-pin shrink plastic molded DIP 42P2R-A ............................................ 42-pin plastic molded SSOP 42S1B-A ................... 42-pin shrink ceramic DIP(EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and EPROM versions.
Memory Size
ROM/PROM size ................................................... 8K to 24K bytes RAM size .............................................................. 512 to 640 bytes
Memory Expansion Plan
ROM size (bytes)
48K
32K
28K
Under development
24K
M38504M6/E6
20K
Mass production
16K
M38503M4/E4
12K
Mass production
8K
M38503M2
128
192
256
384
512 RAM size (bytes)
640
768
896
1024
Products under development or planning : the development schedule and specification may be revised without notice. Planning products may be stopped the development.
Fig. 4 Memory expansion plan Currently planning products are listed below. Table 2 Support products Product name M38503M2-XXXSP M38503M2-XXXFP M38503M4-XXXSP M38503E4-XXXSP M38503E4SP M38503E4SS M38503M4-XXXFP M38503E4-XXXFP M38503E4FP M38504M6-XXXSP M38504E6-XXXSP M38504E6SP M38504E6SS M38504M6-XXXFP M38504E6-XXXFP M38504E6FP (P) ROM size (bytes) ROM size for User in ( ) 8192 (8062) RAM size (bytes) 512 Package 42P4B 42P2R-A 42P4B 16384 (16254) 512 42S1B-A 42P2R-A Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version (stock only replaced by M38504E6SS) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) Remarks As of August 1998
42P4B 32768 (32638) 640 42S1B-A 42P2R-A
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU)
The 3850 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc. The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM : address 003B16)
Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : 0 page 1 : 1 page Not used (return "1" when read) (Do not write "0" to this bit.)
Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available
Fig. 5 Structure of CPU mode register
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
Zero Page
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts. Access to this area with only 2 bytes is possible in the special page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size (bytes) Address XXXX16
000016 SFR area 004016 010016 Zero page
192 256 384 512 640 768 896 1024 1536 2048 3072 4032
00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 0C3F16 0FFF16
RAM
XXXX16 Reserved area 044016 Not used YYYY16 Reserved ROM area
ROM area
ROM size (bytes) Address YYYY16 Address ZZZZ16
(128 bytes)
4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440
F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016
F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016
ZZZZ16
ROM FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Special page
Reserved ROM area
Fig. 6 Memory map diagram
7
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416
Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer XY mode register (TM) Prescaler X (PREX) Timer X (TX) Prescaler Y (PREY) Timer Y (TY) Timer count source selection register (TCSS)
Reserved V Reserved V Reserved V Reserved V Reserved V Reserved V
A-D control register (ADCON) A-D conversion low-order register (ADL) A-D conversion high-order register (ADH)
Reserved V Reserved V Reserved V Transmit/Receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) PWM control register (PWMCON) PWM prescaler (PREPWM) PWM register (PWM) V Reserved : Do not write "1" to this address.
003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 7 Memory map of special function register (SFR)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Table 3 I/O port function Pin P00-P07 P10-P17 P20/XCOUT P21/XCIN P22 P23 Port P2 Serial I/O function I/O Input/output, individual bits Name Port P0 Port P1 CMOS compatible input level CMOS 3-state output CMOS compatible input level N-channel open-drain output Serial I/O control register Serial I/O control register Serial I/O control register Timer XY mode register A-D control register Timer XY mode register Interrupt edge selection register Interrupt edge selection register PWM control register (1) Sub-clock generating circuit (2) (3) (4) Input/Output I/O Structure Non-Port Function Related SFRs Ref.No.
CPU mode register
P24/RxD P25/TxD P26/SCLK
(5) (6) (7)
Serial I/O function I/O Serial I/O function I/O Timer X function I/O A-D conversion input Timer Y function I/O External interrupt input
P27/CNTR0/SRDY P30/AN0- P34/AN4 P40/CNTR1 P41/INT0- P43/INT2 P44/INT3/PWM
CMOS compatible input level CMOS 3-state output Port P3
(8)
(9) (10) (11)
Port P4 External interrupt input PWM output
(12)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0, P1
Direction register
(2) Port P20
Port XC switch bit Direction register
Data bus
Port latch Data bus Port latch
Oscillator Port P21
(3) Port P21
Port XC switch bit Direction register
Port XC switch bit
(4) Port P22, P23
Data bus
Port latch Direction register
Data bus Sub-clock generating circuit input
Port latch
(5) Port P24
Serial I/O enable bit Receive enable bit
(6) Port P25
Direction register P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register
Data bus
Port latch
Data bus Serial I/O input
Port latch
(7) Port P26
Serial I/O clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch
Serial I/O output
(8) Port P27
Pulse output mode Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch
Serial clock output External clock input Pulse output mode Serial ready output Timer output CNTR0 interrupt input
Fig. 8 Port block diagram (1)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P30-P34
Direction register
(10) Port P40
Direction register
Data bus Data bus Port latch
Port latch
Pulse output mode A-D converter input Analog input pin selection bit Timer output CNTR1 interrupt input
(11) Port P41-P43
Direction register
(12) Port P44
PWM output enable bit Direction register
Data bus
Port latch Data bus Port latch
Interrupt input PWM output
Fig. 9 Port block diagram (2)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 14 sources among 14 sources: six external, seven internal, and one software.
sNotes
When the active edge of an external interrupt (INT0-INT3, CNTR0, CNTR1) is set, the corresponding interrupt request bit may also be set. Therefore, take the following sequence: 1. Disable the interrupt 2. Change the interrupt edge selection register (the timer XY mode register for CNTR0 and CNTR1) 3. Clear the interrupt request bit to "0" 4. Accept the interrupt.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are automatically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter.
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 4 Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 Reserved INT1 INT2 INT3 Reserved Timer X Timer Y Timer 1 Timer 2 Serial I/O reception Serial I/O Transmission CNTR0 CNTR1 A-D converter BRK instruction Priority 1 2 3 4 5 6 7 8 9 10 11 12 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input Reserved At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At detection of either rising or falling edge of INT3 input Reserved At timer X underflow At timer Y underflow At timer 1 underflow At timer 2 underflow At completion of serial I/O data reception At completion of serial I/O transfer shift or when transmission buffer is empty At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of A-D conversion At BRK instruction execution Non-maskable software interrupt Valid when serial I/O is selected Valid when serial I/O is selected External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Remarks Non-maskable External interrupt (active edge selectable)
STP release timer underflow
13 14 15 16 17
FFE516
FFE416
FFE316 FFE116 FFDF16 FFDD16
FFE216 FFE016 FFDE16 FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 10 Interrupt control
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 active edge selection bit INT1 active edge selection bit INT2 active edge selection bit INT3 active edge selection bit Reserved(Do not write "1" to this bit) Not used (returns "0" when read)
0 : Falling edge active 1 : Rising edge active
b7
b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit Reserved INT1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Reserved Timer X interrupt request bit Timer Y interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0 Interrupt request register 2 (IREQ2 : address 003D16) Timer 1 interrupt request bit Timer 2 interrupt request bit Serial I/O reception interrupt request bit Serial I/O transmit interrupt request bit CNTR0 interrupt request bit CNTR1 interrupt request bit AD converter interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit Reserved(Do not write "1" to this bit) INT1 interrupt enable bit INT2 interrupt enable bit INT3 interrupt enable bit Reserved(Do not write "1" to this bit) Timer X interrupt enable bit Timer Y interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O reception interrupt enable bit Serial I/O transmit interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit AD converter interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled
Fig. 11 Structure of interrupt-related registers (1)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3850 group has four timers: timer X, timer Y, timer 1, and timer 2. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches "0016", an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1".
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency which is selected by timer 12 count source selection bit. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source selection bit.
b7 b0 Timer XY mode register (TM : address 002316) Timer X operating mode bit b1b0 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR0 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X count stop bit 0: Count start 1: Count stop Timer Y operating mode bit b5b4 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR1 active edge selection bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer Y count stop bit 0: Count start 1: Count stop
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source selection bit. Whenever the contents of the timer reach "0016", the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is "0", output begins at " H". If it is "1", output starts at "L". When using a timer in this mode, set the corresponding port P27 ( or port P40) direction register to output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or CNTR1 pin. When the CNTR0 (or CNTR1) active edge selection bit is "0", the rising edge of the CNTR0 (or CNTR1) pin is counted. When the CNTR0 (or CNTR1) active edge selection bit is "1", the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is "0", the timer counts the selected signals by the count source selection bit while the CNTR0 (or CNTR1) pin is at "H". If the CNTR0 (or CNTR1) active edge selection bit is "1", the timer counts it while the CNTR0 (or CNTR1) pin is at "L". The count can be stopped by setting "1" to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer underflows.
Fig. 12 Structure of timer XY mode register
b7
b0 Timer count source selection register (TCSS : address 002816) Timer X count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer Y count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode) Timer 12 count source selection bit 0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode) 1 : f(XCIN) Not used (returns "0" when read)
sNote
When switching the count source by the timer 12, X and Y count source bit, the value of timer count is altered in unconsiderable amount owing to generating of a thin pulses in the count input signals. Therefore, select the timer count source before set the value to the prescaler and the timer.
Fig. 13 Structure of timer count source selection register
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
f(XIN)/16 f(XIN)/2
Prescaler X latch (8)
Timer X latch (8)
Pulse width Timer X count source selection bit measurement Timer mode Pulse output mode mode Prescaler X (8) CNTR0 active edge selection bit "0" "1" Event counter mode Timer X count stop bit Timer X (8)
To timer X interrupt request bit
P27/CNTR0
To CNTR0 interrupt request bit
CNTR0 active edge selection "1" bit "0"
Q Q
Toggle flip-flop T R Timer X latch write pulse Pulse output mode
Port P27 direction register
Port P27 latch Pulse output mode Data bus
f(XIN)/16 f(XIN)/2 Timer Y count source selection bit
Prescaler Y latch (8) Pulse width measurement mode Timer mode Pulse output mode Prescaler Y (8)
Timer Y latch (8)
Timer Y (8)
P40/CNTR1
CNTR1 active edge selection bit "0" "1"
To timer Y interrupt request bit
Event counter mode
Timer Y count stop bit To CNTR1 interrupt request bit
CNTR1 active edge selection "1" bit "0"
Q Toggle flip-flop T Q R Timer Y latch write pulse Pulse output mode
Port P40 direction register
Port P40 latch
Pulse output mode Data bus
Prescaler 12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
f(XIN)/16 f(XCIN) Timer 12 count source selection bit
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 2 interrupt request bit
To timer 1 interrupt request bit
Fig. 14 Block diagram of timer X, timer Y, timer 1, and timer 2
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register (bit 6 of address 001A16) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
Data bus Address 001816 Receive buffer register P24/RXD Receive shift register Shift clock P26/SCLK Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 Serial I/O control register Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit
XIN
BRG count source selection bit 1/4
P27/SRDY
F/F
Falling-edge detector Shift clock
Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916
P25/TXD
Transmit shift register Transmit buffer register Address 001816 Data bus
Fig. 15 Block diagram of clock synchronous serial I/O
Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Receive enable signal SRDY Write pulse to receive/transmit buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection
TBE = 1 TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 16 Operation of clock synchronous serial I/O function
17
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit (b6) of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
Data bus Address 001816 OE Character length selection bit ST detector 7 bits Receive shift register 8 bits PE FE SP detector Clock control circuit Serial I/O synchronous clock selection bit P26/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 1/4 ST/SP/PA generator 1/16 P25/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI)
Receive buffer register
Serial I/O control register
Address 001A16
Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 UART control register Address 001B16
P24/RXD
XIN
Fig.17 Block diagram of UART serial I/O
18
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write signal TBE=0 TSC=0 TBE=1 TBE=0 TBE=1 TSC=1
Serial output TXD
ST
D0
D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s)
SP
ST
D0
D1
SP Generated at 2nd bit in 2-stop-bit mode
Receive buffer read signal
RBF=0 RBF=1 RBF=1
Serial input RXD
ST
D0
D1
SP
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 18 Operation of UART serial I/O function
[Transmit Buffer Register/Receive Buffer Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0".
Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register consists of eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P25/TXD pin.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1".
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
19
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O status register (SIOSTS : address 0019 16) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read)
b7
b0
Serial I/O control register (SIOCON : address 001A 16) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P27 pin operates as ordinary I/O pin 1: P27 pin operates as S RDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P24 to P27 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P24 to P27 operate as serial I/O pins)
b7
b0
UART control register (UARTCON : address 001B 16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P25/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read)
Fig. 19 Structure of serial I/O control registers
20
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 3850 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to "1", operation starts by initializing the PWM output circuit, and pulses are output starting at an "H". If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made.
Data Setting
The PWM output pin also functions as port P44. Set the PWM period by the PWM prescaler, and set the "H" term of output pulse by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 ! (n+1) / f(XIN) = 31.875 ! (n+1) s (when f(XIN) = 8 MHz) Output pulse "H" term = PWM period ! m / 255 = 0.125 ! (n+1) ! m s (when f(XIN) = 8 MHz)
31.875 ! m ! (n+1) s 255 PWM output T = [31.875 ! (n+1)] s m: Contents of PWM register n : Contents of PWM prescaler T : PWM period (when f(X IN) = 8 MHz)
Fig. 20 Timing of PWM period
Data bus
PWM prescaler pre-latch
PWM register pre-latch
Transfer control circuit
PWM prescaler latch Count source selection bit XIN 1/2 "0" "1" PWM prescaler
PWM register latch
Port P44 PWM register
Port P44 latch
PWM enable bit
Fig. 21 Block diagram of PWM function
21
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register (PWMCON : address 001D16) PWM function enable bit 0: PWM disabled 1: PWM enabled Count source selection bit 0: f(XIN) 1: f(XIN)/2 Not used (return "0" when read)
Fig. 22 Structure of PWM control register
A PWM output T PWM register write signal
B
C
B= C T2 T
T (Changes "H" term from "A" to "B".)
T2
PWM prescaler write signal
(Changes PWM period from "T" to "T2".)
When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change.
Fig. 23 PWM output timing when PWM register or PWM prescaler is changed
sNote
The PWM starts after the PWM enable bit is set to enable and "L" level is output from the PWM pin. The length of this "L" level output is as follows:
n+1 2 * f(XIN) n+1 f(XIN)
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
sec
(Count source selection bit = 1, where n is the value set in the prescaler)
22
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER [A-D Conversion Registers (ADL, ADH)] 003516, 003616
The A-D conversion registers are read-only registers that store the result of an A-D conversion. Do not read these registers during an A-D conversion
b7
b0
AD control register (ADCON : address 003416) Analog input pin selection bits
b2 b1 b0
[AD Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 4 indicates the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion and changes to "1" when an A-D conversion ends. Writing "0" to this bit starts the A-D conversion.
0 0 0 0 1
0 0 1 1 0
0: P30/AN0 1: P31/AN1 0: P32/AN2 1: P33/AN3 0: P34/AN4
Not used (returns "0" when read) A-D conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns "0" when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF into 1024 and outputs the divided voltages. Fig. 24 Structure of AD control register
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4 and inputs the voltage to the comparator.
10-bit reading (Read address 003616 before 003516)
b7
Comparator and Control Circuit
The comparator and control circuit compare an analog input voltage with the comparison voltage, and the result is stored in the A-D conversion registers. When an A-D conversion is completed, the control circuit sets the A-D conversion completion bit and the A-D interrupt request bit to "1". Note that because the comparator consists of a capacitor coupling, set f(XIN) to 500 kHz or more during an A-D conversion.
(Address 003616)
b7
b0 b9 b8 b0
(Address 003516) b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 0036 16 become "0" at reading.
8-bit reading (Read only address 003516)
b7 b0
(Address 003516) b9 b8 b7 b6 b5 b4 b3 b2
Fig. 25 Structure of A-D conversion registers
Data bus
AD control register (Address 0034 16)
b7
b0
3 P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 A-D control circuit A-D interrupt request
Channel selector
Comparator
A-D conversion high-order register (Address 0036 16) A-D conversion low-order register (Address 0035 16) 10 Resistor ladder
VREF AVSS
Fig. 26 Block diagram of A-D converter
23
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control register (address 003916) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 003916) and an internal reset occurs at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 003916) may be started before an underflow. When the watchdog timer control register (address 003916) is read, the values of the high-order 6 bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. qInitial value of watchdog timer At reset or writing to the watchdog timer control register (address 003916), each watchdog timer H and L is set to "FF16."
qWatchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 003916) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set to 131.072 ms at f(XIN) = 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to 512 s at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN) = 32 kHz frequency. This bit is cleared to "0" after resetting. qOperation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 003916) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled, once the STP instruction is executed, an internal reset occurs. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting.
XCIN "10" Main clock division ratio selection bits (Note) XIN
"FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/16 "00" "01" "1" Watchdog timer H (8)
Data bus "FF16" is set when watchdog timer control register is written to.
Watchdog timer H count source selection bit
STP instruction disable bit STP instruction Reset circuit Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 27 Block diagram of Watchdog timer
b7
b0
Watchdog timer control register (WDTCON : address 003916)
Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16
Fig. 28 Structure of Watchdog timer control register
24
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage must be between 2.7 V and 5.5 V, and the oscillation must be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V.
Poweron Power source voltage 0V Reset input voltage 0V (Note)
RESET
VCC
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC Power source voltage detection circuit
Fig. 29 Reset circuit example
XIN
RESET
RESETOUT
Address
?
?
?
?
FFFC
FFFD
ADH,L
Reset address from the vector table.
Data
?
?
?
?
ADL
ADH
SYNC
XIN: 8 to 13 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN) = 2 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. 3: All signals except XIN and RESET are internals.
Fig. 30 Reset sequence
25
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents (1) (2) (3) (4) (5) (6) (7) (8) (9) Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P4 direction register (P4D) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) PWM control register (PWMCON) 000116 000316 000516 000716 000916 0016 0016 0016 0016 0016
001916 1 0 0 0 0 0 0 0 001A16 0016
001B16 1 1 1 0 0 0 0 0 001D16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002C16 002D16 002E16 002F16 003016 0016 FF16 0116 0016 0016 FF16 FF16 FF16 FF16 0016 Not fixed Not fixed Not fixed Not fixed Not fixed
(10) Prescaler 12 (PRE12) (11) Timer 1 (T1) (12) Timer 2 (T2) (13) Timer XY mode register (TM) (14) Prescaler X (PREX) (15) Timer X (TX) (16) Prescaler Y (PREY) (17) Timer Y (TY) (18) Timer count source select register (19) Reserved (20) Reserved (21) Reserved (22) Reserved (23) Reserved (24) AD control register (ADCON) (25) MISRG (26) Watchdog timer control register (WDTCON) (27) Interrupt edge selection register (INTEDGE) (28) CPU mode register (CPUM) (29) Interrupt request register 1 (IREQ1) (30) Interrupt request register 2 (IREQ2) (31) Interrupt control register 1 (ICON1) (32) Interrupt control register 2 (ICON2) (33) Processor status register (34) Program counter Note : X indicates Not fixed .
003416 0 0 0 1 0 0 0 0 003816 0016
003916 0 0 1 1 1 1 1 1 003A16 0016
003B16 0 1 0 0 1 0 0 0 003C16 003D16 003E16 003F16 0016 0016 0016 0016
(PS) X X X X X 1 X X (PCH) (PCL)
FFFD16 contents FFFC16 contents
Fig. 31 Internal status at reset
26
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3850 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after power on, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports.
be generated.
(2) Wait mode
If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that the interrupts will be received to release the STP or WIT state, their interrupt enable bits must be set to "1" before executing of the STP or WIT instruction. When releasing the STP state, the prescaler 12 and timer 1 will start counting the clock XIN divided by 16. Accordingly, set the timer 1 interrupt enable bit to "0" before executing the STP instruction.
Frequency Control (1) Middle-speed mode
The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected.
(2) High-speed mode
The internal clock is half the frequency of XIN.
sNote
When using the oscillation stabilizing time set after STP instruction released bit set to "1", evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
(3) Low-speed mode
The internal clock is half the frequency of XCIN.
sNote
If you switch the mode between middle/high-speed and lowspeed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from the stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3*f(XCIN).
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set sufficient time for oscillation to stabilize. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate.
CCIN CIN COUT
Fig. 32 Ceramic resonator circuit
Oscillation Control (1) Stop mode
If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillation stops. When the oscillation stabilizing time set after STP instruction released bit is "0," the prescaler 12 is set to "FF16" and timer 1 is set to "0116." When the oscillation stabilizing time set after STP instruction released bit is "1," set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. Either XIN or XCIN divided by 16 is input to the prescaler 12 as count source. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 1 underflows. The internal clock is supplied for the first time, when timer 1 underflows. This ensures time for the clock oscillation using the ceramic resonators to be stabilized. When the oscillator is restarted by reset, apply "L" level to the RESET pin until the oscillation is stable since a wait time will not
XCIN Rf
XCOUT Rd CCOUT
XIN
XOUT Open
External oscillation circuit CCIN Vcc Vss
Fig. 33 External clock input circuit
27
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Middle-speed mode automatic switch set bit
MISRG (MISRG : address 003816) Oscillation stabilizing time set after STP instruction released bit 0: Automatically set "0116" to Timer 1, "FF16" to Prescaler 12 1: Automatically set nothing Middle-speed mode automatic switch set bit 0: Not set automatically 1: Automatic switching enable Middle-speed mode automatic switch wait time set bit 0: 4.5 to 5.5 machine cycles 1: 6.5 to 7.5 machine cycles Middle-speed mode automatic switch start bit (Depending on program) 0: Invalid 1: Automatic switch start Not used (return "0" when read)
By setting the middle-speed mode automatic switch set bit to "1" while operating in the low-speed mode, XIN oscillation automatically starts and the mode is automatically switched to the middle-speed mode when defecting a rising/falling edge of the SCL or SDA pin. The middle-speed automatic switch wait time set bit can select the switch timing from the low-speed to the middlespeed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5 machine cycles in the low-speed mode. Select it according to oscillation start characteristics of used XIN oscillator. The middle-speed mode automatic switch start bit is used to automatically make to XIN oscillation start and switch to the middle-speed mode by setting this bit to "1" while operating in the low-speed mode.
Fig. 34 Structure of MISRG
XCIN
XCOUT
"1"
"0"
Port XC switch bit
XIN
XOUT
Main clock division ratio selection bits (Note) Low-speed mode
1/2
High-speed or middle-speed mode
1/4
1/2
Prescaler 12 FF16
Timer 1 0116
Reset or STP instruction
Main clock division ratio selection bits (Note) Middle-speed mode High-speed or low-speed mode Main clock stop bit
Timing (internal clock)
Q
S R
STP instruction WIT instruction
SQ R
QS R
STP instruction
Reset Interrupt disable flag l Interrupt request
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register. When low-speed mode is selected, set port Xc switch bit (b1) to "1".
Fig. 35 System clock generating circuit block diagram (Single-chip mode)
28
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode (f()=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped)
CM6 "1""0"
High-speed mode (f()=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=0(32 kHz stopped)
CM " 0" "1 M6 " C " "1
4
"0
"
C "0 M4 " C "1 M6 " 1" " "0 "
CM4 "1""0"
Middle-speed mode (f()=1 MHz) CM7=0 CM6=1 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
CM6 "1""0"
High-speed mode (f()=4 MHz) CM7=0 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
"
"0
"
Low-speed mode (f()=16 kHz) CM7=1 CM6=0 CM5=0(8 MHz oscillating) CM4=1(32 kHz oscillating)
CM7 "1""0"
"1
"
C "0 M7 CM "
6
"1
CM4 "1""0"
b7
b4 CPU mode register (CPUM : address 003B 16)
Low-speed mode (f()=16 kHz) CM7=1 CM6=0 CM5=1(8 MHz stopped) CM4=1(32 kHz oscillating)
CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7, CM6: Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 ( High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : Timer operates in the wait mode. 4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 in middle/high-speed mode. 5 : When the stop mode is ended, a delay of approximately 16 ms occurs by Timer 1 and Timer 2 in low-speed mode. 6 : Wait until oscillation stabilizes after oscillating the main clock X IN before the switching from the low-speed mode to middle/high-speed mode. 7 : The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. indicates the internal clock.
Fig. 36 State transitions of system clock
CM5 "1""0"
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency in high-speed mode.
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * The data transfer instruction (LDA, etc.) * The operation instruction when the index X mode flag (T) is "1" * The addressing mode which uses the value of a direction register as an index * The bit-test instruction (BBC or BBS, etc.) to a direction register * The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to "1." Serial I/O continues to output the final bit from the TXD pin after transmission is completed. When an external clock is used as synchronous clock in serial I/O, write transmission data to the transmit buffer register while the transfer clock is "H."
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: 1.Mask ROM Order Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table 5 Programming adapter
DATA R E QU I R E D F O R RO M W R I T I N G ORDERS
The following are necessary when ordering a ROM writing: 1.ROM Writing Confirmation Form 2.Mark Specification Form 3.Data to be written to ROM, in EPROM form (three identical copies)
Package 42P2R-A 42P4B
Name of Programming Adapter PCA4738F-42A PCA4738S-42A
The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 49 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150 C for 40 hours)
Verification with PROM programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours.
Fig. 37 Programming and testing of One Time PROM version
31
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 6 Absolute maximum ratings Symbol VCC VI VI VI VI VO VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P24-P27, P30-P34, VREF Input voltage P22, P23 Input voltage RESET, XIN Input voltage CNVSS Output voltage P00-P07, P10-P17, P24-P27, P30-P34, XOUT Output voltage P22, P23 Power dissipation Operating temperature Storage temperature Conditions P20, P21, P40-P44, All voltages are based on VSS. Output transistors are cut off. P20, P21, P40-P44, Ratings -0.3 to 7.0 -0.3 to VCC +0.3 -0.3 to 5.8 -0.3 to VCC +0.3 -0.3 to 13 -0.3 to VCC +0.3 -0.3 to 5.8 300 -20 to 85 -40 to 125 Unit V V V V V V V mW C C
Ta = 25 C
Table 7 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC VSS VREF AVSS VIA VIH VIH VIL VIL VIL IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Parameter Power source voltage (At 8 MHz) Power source voltage (At 4 MHz) Power source voltage A-D convert reference voltage Analog power source voltage Analog input voltage AN0-AN4 "H" input voltage "H" input voltage "L" input voltage "L" input voltage "L" input voltage "H" total peak output current "H" total peak output current "L" total peak output current "L" total peak output current "L" total peak output current "H" total average output current "H" total average output current "L" total average output current "L" total average output current "L" total average output current P00-P07, P10-P17, P20-P27, P30-P34, P40-P44 RESET, XIN, CNVSS P00-P07, P10-P17, P20-P27, P30-P34, P40-P44 RESET, CNVSS XIN P00-P07, P10-P17, P30-P34 (Note) P20, P21, P24-P27, P40-P44 (Note) P00-P07, P10-P12, P30-P34 (Note) P13-P17 (Note) P20-P27,P40-P44 (Note) P00-P07, P10-P17, P30-P34 (Note) P20, P21, P24-P27, P40-P44 (Note) P00-P07, P10-P12, P30-P34 (Note) P13-P17 (Note) P20-P27,P40-P44 (Note) Min. 4.0 2.7 2.0 0 AVSS 0.8VCC 0.8VCC 0 0 0 VCC VCC VCC 0.2VCC 0.2VCC 0.16VCC -80 -80 80 80 80 -40 -40 40 40 40 Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents.
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Recommended operating conditions (2) (VCC = 2.7 to 5.5 V, Ta = -20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) f(XIN) "H" peak output current Parameter P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 (Note 1) "L" peak output current P00-P07, P10-P12, P20-P27, P30-P34, P40-P44 (Note 1) "L" peak output current P13-P17 (Note 1) "H" average output current P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 (Note 2) "L" average output current P00-P07, P10-P12, P20-P27, P30-P34, P40-P44 (Note 2) "L" peak output current P13-P17 (Note 2) Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3) Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3) Min. Limits Typ. Max. -10 10 20 -5 5 15 8 4 Unit mA mA mA mA mA mA MHz kHz
Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50%.
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 9 Electrical characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol Parameter "H" output voltage P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 (Note) "L" output voltage P00-P07, P10-P12, P20-P27 P30-P34, P40-P44 "L" output voltage P13-P17 Test conditions IOH = -10 mA VCC = 4.0-5.5 V IOH = -1.0 mA VCC = 2.7-5.5 V IOL = 10 mA VCC = 4.0-5.5 V IOL = 1.0 mA VCC = 2.7-5.5 V IOL = 20 mA VCC = 4.0-5.5 V IOL = 10 mA VCC = 2.7-5.5 V Min. VCC-2.0 VCC-1.0 2.0 1.0 2.0 1.0 0.4 0.5 0.5 VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped 4 -5.0 -5.0 -4 2.0 5.5 5.0 5.0 Typ. Max. Unit V V V V V V V V V A A A A A A V
VOH
VOL
VOL
VT+-VT- VT+-VT- VT+-VT- IIH IIH IIH IIL IIL IIL VRAM
Hysteresis CNTR0, CNTR1, INT0-INT3 Hysteresis RxD, SCLK Hysteresis RESET "H" input current P00-P07, P10-P17, P20, P21, P24-P27, P30-P34, P40-P44 "H" input current RESET, CNVSS "H" input current XIN "L" input current P00-P07, P10-P17, P20-P27 P30-P34, P40-P44 "L" input current RESET,CNVSS "L" input current XIN RAM hold voltage
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0".
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 10 Electrical characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Limits Parameter Test conditions High-speed mode f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors "off" High-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors "off" Low-speed mode (VCC = 3 V) f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors "off" Middle-speed mode f(XIN) = 8 MHz f(XCIN) = stopped Output transistors "off" Middle-speed mode f(XIN) = 8 MHz (in WIT state) f(XCIN) = stopped Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8 MHz All oscillation stopped (in STP state) Output transistors "off" Ta = 25 C Ta = 85 C Min. Typ. 6.8 Max. 13 Unit
mA
1.6
mA
60
200
A
20
40
A
ICC
Power source current
20
55
A
5.0
10.0
A
4.0
7.0
mA
1.5
mA
800 0.1 1.0 10
A A A
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 11 A-D converter characteristics (VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 85 C, f(XIN) = 8 MHz, unless otherwise noted) Symbol - - tCONV RLADDER IVREF II(AD) Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current Test conditions Limits Min. Typ. Max. 10 4 61 200 5.0 Unit bit LSB tc() k A A
VREF = 5.0 V
50
35 150 0.5
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 12 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1, INT0-INT3 input "H" pulse width CNTR0, CNTR1, INT0-INT3 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input setup time Serial I/O input hold time Min. 2 125 50 50 200 80 80 800 370 370 220 100 Limits Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART).
Table 13 Timing requirements (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RxD-SCLK) th(SCLK-RxD) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1, INT0-INT3 input "H" pulse width CNTR0, CNTR1, INT0-INT3 input "L" pulse width Serial I/O clock input cycle time (Note) Serial I/O clock input "H" pulse width (Note) Serial I/O clock input "L" pulse width (Note) Serial I/O input setup time Serial I/O input hold time Limits Min. 2 250 100 100 500 230 230 2000 950 950 400 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is "0" (UART).
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK) tWL (SCLK) td (SCLK-TXD) tv (SCLK-TXD) tr (SCLK) tf (SCLK) tr (CMOS) tf (CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. Typ. tC(SCLK)/2-30 tC(SCLK)/2-30 140 -30 30 30 30 30 Max. Unit ns ns ns ns ns ns ns ns
10 10
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: The XOUT pin is excluded.
Table 15 Switching characteristics 2 (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH (SCLK) tWL (SCLK) td (SCLK-TXD) tv (SCLK-TXD) tr (SCLK) tf (SCLK) tr (CMOS) tf (CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Limits Min. Typ. tC(SCLK)/2-50 tC(SCLK)/2-50 -30 50 50 50 50 Max. Unit ns ns ns ns ns ns ns ns
350
20 20
Notes 1: For tWH(SCLK), tWL(SCLK), when the P51/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: The XOUT pin is excluded.
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1k Measurement output pin Measurement output pin 100pF 100pF CMOS output
N-channel open-drain output
Fig. 38 Circuit for measuring output switching characteristics (1)
Fig. 39 Circuit for measuring output switching characteristics (2)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC
CNTR0, CNTR1
0.8VCC
tWH(INT)
tWL(INT) 0.2VCC
INT0 to INT3
0.8VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC
XIN
0.8VCC
tf
tWL(SCLK) 0.2VCC
tC(SCLK) tr 0.8VCC
tWH(SCLK)
SCLK
tsu(RxD-SCLK)
th(SCLK-RxD)
RXD
td(SCLK-TXD)
0.8VCC 0.2VCC tv(SCLK-TXD)
TXD
Fig. 40 Timing diagram
40
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MASK ROM CONFIRMATION FORM
GZZ-SH53-11B<86A0>
Mask ROM number
Note : Please fill in all items marked g.
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
g Customer
)
Date issued
Date:
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name: M38503M2-XXXSP M38503M2-XXXFP
Checksum code for entire EPROM EPROM type (indicate the type used)
Issuance signature
Company name
TEL (
Submitted by
Supervisor
(hexadecimal notation)
27256
EPROM address 000016 Product name 000F16 001016 607F16 608016 7FFD16 7FFE16 7FFF16
ASCII code : `M38503M2-'
27512
EPROM address 000016 Product name 000F16 001016 E07F16 E08016 FFFD16 FFFE16 FFFF16
ASCII code : `M38503M2-'
In the address space of the microcomputer, the internal ROM area is from address 608016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16.
data ROM (8K-130) bytes
data ROM (8K-130) bytes
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38503M2-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716 (1/2)
`M' = 4D16 `3' = 3316 `8' = 3816 `5' = 3516 `0' = 3016 `3' = 3316 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
`-' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
41
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH53-11B<86A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M2-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM. EPROM type The pseudo-command 27256 *= $8000 .BYTE `M38503M2-' 27512 *= $0000 .BYTE `M38503M2-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M38503M2-XXXSP, 42P2R-A for M38503M2-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz
(2) Which function will you use the pins P21/XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ? Ports P21 and P20 function g 4. Comments XCIN and XCOUT function (external resonator)
(2/2)
42
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MASK ROM CONFIRMATION FORM
GZZ-SH11-40A<6YA0>
Mask ROM number
Note : Please fill in all items marked g.
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
g Customer
)
Date issued
Date:
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name: M38503M4-XXXSP M38503M4-XXXFP
Checksum code for entire EPROM EPROM type (indicate the type used)
Issuance signature
Company name
TEL (
Submitted by
Supervisor
(hexadecimal notation)
27256
EPROM address 000016 Product name 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16
ASCII code : `M38503M4-'
27512
EPROM address 000016 Product name 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16
ASCII code : `M38503M4-'
In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16.
data ROM (16K-130) bytes
data ROM (16K-130) bytes
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38503M4-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716 (1/2)
`M' = 4D16 `3' = 3316 `8' = 3816 `5' = 3516 `0' = 3016 `3' = 3316 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
`-' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
43
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-40A<6YA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503M4-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM. EPROM type The pseudo-command 27256 *= $8000 .BYTE `M38503M4-' 27512 *= $0000 .BYTE `M38503M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form (42P4B for M38503M4-XXXSP, 42P2R-A for M38503M4-XXXFP) and attach it to the mask ROM confirmation form. g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz
(2) Which function will you use the pins P21/XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ? Ports P21 and P20 function g 4. Comments XCIN and XCOUT function (external resonator)
(2/2)
44
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ROM PROGRAMMING CONFIRMATION FORM
GZZ-SH11-41A<6YA0>
ROM number
Note : Please fill in all items marked g.
Receipt
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP MITSUBISHI ELECTRIC
Date: Section head Supervisor signature signature
g Customer
)
Date issued
Date:
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the programming data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name: M38503E4-XXXSP M38503E4-XXXFP (hexadecimal notation)
Checksum code for entire EPROM
EPROM type (indicate the type used)
27256
EPROM address 000016 Product name 000F16 001016 407F16 408016 7FFD16 7FFE16 7FFF16
ASCII code : `M38503E4-'
27512
EPROM address 000016 Product name 000F16 001016 C07F16 C08016 FFFD16 FFFE16 FFFF16
ASCII code : `M38503E4-'
In the address space of the microcomputer, the internal ROM area is from address C08016 to FFFD16. The reset vector is stored in addresses FFFC16 and FFFD16.
data ROM (16K-130) bytes
data ROM (16K-130) bytes
Issuance signature
Company name
TEL (
Submitted by
Supervisor
(1) Set the data in the unused area (the shaded area of the diagram) to "FF16". (2) The ASCII codes of the product name "M38503E4-" must be entered in addresses 000016 to 000816. And set the data "FF16" in addresses 000916 to 000F16. The ASCII codes and addresses are listed to the right in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716 (1/2)
`M' = 4D16 `3' = 3316 `8' = 3816 `5' = 3516 `0' = 3016 `3' = 3316 `E' = 4516 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
`-' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH11-41A<6YA0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M38503E4-XXXSP/FP MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM. EPROM type The pseudo-command 27256 *= $8000 .BYTE `M38503E4-' 27512 *= $0000 .BYTE `M38503E4-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM will not be processed. g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Fill out the appropriate mark specification form; 42P2R-A for the M38503E4-XXXFP, the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M38503E4-XXXSP; and attach it to the ROM programming confirmation form.
g 3. Usage conditions Please answer the following questions about usage for use in our product inspection : (1) How will you use the XIN-XOUT oscillator? Ceramic resonator External clock input At what frequency? Quartz crystal Other ( f(XIN) = ) MHz
(2) Which function will you use the pins P21/XCIN and P20/XCOUT as P21 and P20, or XCIN and XCOUT ? Ports P21 and P20 function g 4. Comments XCIN and XCOUT function (external resonator)
(2/2)
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MARK SPECIFICATION FORM
47
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
48
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SHRINK DIP MARK SPECIFICATION FORM for One Time PROM version microcomputers
Enter the catalog number of the microcomputer for which this mark specification is intended. (If you do not know the ROM code number, enter XXX in its place.) The catalog number of the microcomputer
M
A. Standard Mitsubishi Mark Customer specified part number will be printed together with the ROM code number on the top line. Enter the desired part number left aligned in the box below. (up to 10 characters)
Note2 :
RXXX
Mitsubishi catalog name (blank model number before writing) Mitsubishi lot number (6-digit or 7-digit)
Note1 : The following characters can be used in the part number : Uppercase alphabet, numbers, ampersand, hyphen, period, comma, +, /, (, ), (c) ((c) will be printed at 1.5 x character width) 2 : XXX is the ROM code number. B. Special Mark Required If you desire anything other than the standard Mitsubishi mark, it will be treated as a special mark. Special marks will take longer to produce and should be avoided if possible. If a special mark is to be printed, indicate the desired layout of the mark in the figure below. The layout will be duplicated as closely as possible.
Note1 : If the customer's trademark logo must be used in the Special Mark, please submit a clean original logo. Note that special marks require extra cost and time to produce.
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MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
42P2R-A
EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code - Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 450mil SSOP
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42 22
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HE
E
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Recommended Mount Pad Symbol Dimension in Millimeters Min Nom Max - - 2.4 0.05 - - - 2.0 - 0.35 0.4 0.5 0.13 0.15 0.2 17.3 17.5 17.7 8.2 8.4 8.6 - 0.8 - 11.63 11.93 12.23 0.3 0.5 0.7 - 1.765 - - - 0.15 0 - 10 - 0.5 - - 11.43 - - 1.27 -
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D
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b
c Detail F
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A A1 A2 b c D E e HE L L1 y b2 e1 I2
42P4B
EIAJ Package Code SDIP42-P-600-1.78 JEDEC Code - Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy
Plastic 42pin 600mil SDIP
42
22
1
21
Symbol D A A1 A2 b b1 b2 c D E e e1 L
e SEATING PLANE
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Dimension in Millimeters Min Nom Max - - 5.5 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 - 1.778 - - 15.24 - 3.0 - - 0 - 15
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I2
MITSUBISHI MICROCOMPUTERS
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42S1B-A
EIAJ Package Code WDIP42-C-600-1.78 JEDEC Code - Weight(g)
Metal seal 42pin 600mil DIP
D
42 22
c
Symbol A A1 A2 b b1 c D E e e1 L Z Dimension in Millimeters Min Nom Max - - 5.0 - - 1.0 3.44 - - 0.38 0.54 0.46 0.7 0.8 0.9 0.17 0.33 0.25 - - 41.1 - 15.8 - - - 1.778 - - 15.24 3.05 - - - - 3.05
1
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L
A
Z
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b
b1 SEATING PLANE
Keep safety first in your circuit designs!
q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
(c) 1998 MITSUBISHI ELECTRIC CORP. New publication, effective Aug. 1998. Specifications subject to change without notice.
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REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
3850 GROUP DATA SHEET
Revision Description Rev. date 980817
(1/1)

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